hoteagle
Newbie level 5
I am now do a SAR ADC design and need to do mixed-signal simulation on my design.
The digital part of the circuit is descripted with VerilogHDL at RTL level. And then I make it as a symbol and integrated into a schemetic with analog part. The stimulus to digital part is descripted with verilogHDL and the stimulus to analog part is directly added on the schemetic. And then I run the simulation with Cadence mixed-signal simulator. No error or warning reported, but no waveform output.
Would you help me to give an explanation?
The digital part of the circuit is descripted with VerilogHDL at RTL level. And then I make it as a symbol and integrated into a schemetic with analog part. The stimulus to digital part is descripted with verilogHDL and the stimulus to analog part is directly added on the schemetic. And then I run the simulation with Cadence mixed-signal simulator. No error or warning reported, but no waveform output.
Would you help me to give an explanation?
