How to do LVS of digital circuit in verilogHDL with Calibre?

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sharpsheep

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We are now doing mixed signal layout lvs. The digital circuit is described with verilogHDL, while calibre can only recongnize cdl netlist. How can I deal with this lvs problem? How can I translate verilogHDL to spice netlist?

Thanks a lot!
 

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