How to do LVS of digital circuit in verilogHDL with Calibre?

[sharpsheep]

We are now doing mixed signal layout lvs. The digital circuit is described with verilogHDL, while calibre can only recongnize cdl netlist. How can I deal with this lvs problem? How can I translate verilogHDL to spice netlist?

Thanks a lot!

 

[hung_wai_ming@hotmail.com]

There is a command, "v2lvs" in calibre to convert verilog HDL into spice netlist