how to do LVDS to LVTTL signal conversion in FPGA?

[brahmi15]

Hello,

I am new FPGA. And yes we are using bank 12 and bank 13 which are PL-side HR banks. From the ADRV9361-z7035 both are using LVDS conversion and it goes into the bank 35. We have to route the signal from Bank 35 to bank 12 or 13 to connect external device for that we want to do LVDS to LVTTL conversion.

Kindly guide me step by step how should i do program in Vivado for this application?

Waiting for your response.

Thank you.

 

[KlausST]

Hi,

I don't think you want to configure the ADRV for LVDS or not.

So please tell us what FPGA you want to configure....And what IDE / Software you use and what language.

Usually FPGAs are internally routed single ended, not LVDS, just the I/O buffers may be configured to translate to LVDS.
There may be several ways to do this, either in your code or in the I/O description files.
There may be restrictions which pins / pin pairs to use, additionally the according bank supply may fit to the desired I/O standard.

Klaus

 

[brahmi15]

Hello Klaus,

Thank you for your reply.

I see that the ADRV9361-Z7035 uses the Xilinx XC7Z035-L2 FBG676I. From UG865 we find that banks 12 and 13 of the Z7035 are PL-side HR banks.

We are using vivado design suite 2018.3 and verilog language.

From the ADRV9361-z7035 both are using LVDS conversion and it goes into the bank 35. We have to route the signal from Bank 35 to bank 12 or 13 to connect external device for that we want to do LVDS to LVTTL conversion.
We have 6pair of pins are as transmitter and 6pair of pins are as receiver. Could you show me some example code which is relevant with my requirement?

I have to use IBUFDS for converting the input LVDS to LVTTL and OBUFDS for output signal and clock ?

Thank you

 

[FvM]

The code is simply

outputpins <= inputpins;

LVDS IO standard has to be assigned to inputpins and LVTTL to outputpins.

 

[brahmi15]

Every pins i need to define?

 

[KlausST]

Hi,

Did you read help / documentation?
Or http://www.xilinx.com/support/answers/9462.html
Or http://forums.xilinx.com/t5/Etherne...igns-for-LVDS-FPGA-to-FPGA-Connect/td-p/57410

Klaus

 

[brahmi15]

Yes i read the mentioned help/documentation but i didn't get exact idea.
kindly help.

 

[KlausST]

Hi,

Every pins i need to define?

For sure. I can´t think of any alternative. The compiler needs to know which signal comes/goes to which pin and what I/O standard it needs to have.
There may be a default I/O standard....

I can´t write code, just can read it a bit.
So show what you have done so far. Your first trials and the results.
And please give a linke which document/example you refer to.

Klaus

 

[brahmi15]

Hi,

Kindly find the attached link which i referred.

http://zedboard.org/sites/default/files/documentations/PicoZed%20SDR%202x2%20SOM%20User's%20Guide%20v1.7_0.pdf

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

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Code Verilog - [expand]
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module Lvds_io (
    input wire RX0_P,
    input wire RX0_N,
    output wire TX0_P,
    output wire TX0_N,
);
 
wire  rx0;
 
IBUFDS ibuf_rx0 (
   .I   (RX0_P),
   .I_B (RX0_N),
   .O   (rx0)
);
 
OBUFDS obuf_tx0 (
   .I    (rx0),
   .O    (TX0_P),
   .O_B  (TX0_N)
);
 
endmodule

---

I am trying this attached code.

 

[ads-ee]

And what is your question about this code?

The posted code correctly connects an LVDS input to an LVDS output as long as that is they are the correct primitives for the part family you are using.

 

[brahmi15]

Hi ads-ee,

Thank you for your reply.

I want to connect an LVDS input to an LVTTL output . Please guide with an example how should I do it?

 

[ads-ee]

You already know how to do this as you already know how to write code with instantiated LVDS buffers, just change what primitive you use.

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module lvds_to_se (
    input  wire rx_p,
    input  wire rx_n,
    output wire tx_se,
);
 
    wire  rx0;
 
    // input LVDS to internal single ended signal
    IBUFDS ibufds_inst (
        .I   (rx_p),
        .I_B (rx_n),
        .O   (rx)
    );
 
    // internal single ended signal (rx) to single ended output
    OBUF obuf_inst
        .I   (rx),
        .O   (tx_se)
    );
 
endmodule

---

Or you can connect the output without resorting to using a instantiated OBUF.

---

Code Verilog - [expand]
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module lvds_to_se (
    input  wire rx_p,
    input  wire rx_n,
    output wire tx_se,
);
 
    // input LVDS to single ended signal
    IBUFDS ibufds_inst (
        .I   (rx_p),
        .I_B (rx_n),
        .O   (tx_se) // just route the output of the primitive to an
                     // inferred OBUF by connecting to the output port
    );
 
endmodule

---

 

[brahmi15]

Hello ads-ee,

Thank you for your reply.

Kindly find the below pin configuration of my code.

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module lvds_to_single_ended(
input rx_clk_in_p, // data_clk_p
input rx_clk_in_n, // data_clk_n
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
output tx_clk_out_p, // fb_clk_p
output tx_clk_out_n, // fb_clk_n
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n
);
wire rx_clk_in;
wire tx_clk_out;
wire rx_data_in;
wire tx_data_out;
wire rx_frame_in;
wire tx_frame_out;
 
endmodule

---

Please guide me how to map these signals into IBUFDS and OBUF?

Waiting for your response.

Thank you.

 

[ads-ee]

I already showed you how to write the code, I don't have a clue what you want now given the posted code only hasl differential ports, so there is no way to map anything external to a single ended port.

Draw a picture since you can't seem to tell us what you are trying to do and the code you keep posting conflicts with the descriptions you have written in this thread. Make the drawing detailed with the expected connections and how the FPGA fits in the system.