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abhi_k11 said:I have actually done functional coverage for verilog desing using system verilog. Ncverilog supports system verilog. The same thing I want to do for my vhdl design. I have gone through ncvhdl docs and found that system verilog constructs are not supported. Do I have to use mixed languages simulation for this purpose?
I just want to know how to proceed and do functional coverage for vhdl design using system verilog.
Please let me know.