for functional coverage,you should first cordinate with the design team to list the function point in the spec ,then the tool is easy to use! The most important is the define of the function point!
I have actually done functional coverage for verilog desing using system verilog. Ncverilog supports system verilog. The same thing I want to do for my vhdl design. I have gone through ncvhdl docs and found that system verilog constructs are not supported. Do I have to use mixed languages simulation for this purpose?
I just want to know how to proceed and do functional coverage for vhdl design using system verilog.
I have actually done functional coverage for verilog desing using system verilog. Ncverilog supports system verilog. The same thing I want to do for my vhdl design. I have gone through ncvhdl docs and found that system verilog constructs are not supported. Do I have to use mixed languages simulation for this purpose?
I just want to know how to proceed and do functional coverage for vhdl design using system verilog.
As such VHDL language doesn't support func cov and hence you need to use mixed language sim - SV has bind that can be bound to VHDL (in Questa & VCSMX - not sure of IUS).