how to do ECO? where can I find doc for it?

[sweesw]

where does ECO fit in the whole ASIC design flow? what specific actions should we take for the ECO(e.g, reserver spare cells)?

 

[giggs11]

hi,

ECO stands for Engineering Change Orders which covers the prospects of late changei in specifications or functionality of designed systems. These changes potentially may involve a lot of time for re-work on the designs. However with ECO, one can actually minimize the amount of time and work involved to compensate these changes.

For instance, say that one has completely designed and verified a HDL modelling of a system and has also synthesized after long efforts to achieve certain design metrics. The design has now matured to P&R stage and after obtaining satisfactory layouts through P&R, changes are made to the speed specs or even the functiionality. Now, these changes may not require re-work on the entire system design but merely a portion of it. ECO can track thes changes and tie-up with the other EDA tools to confine the changed circuit area and avoid a complete re-work of the entire design.

Hope the explanation helps.

 

[kidman]

So there is an tool for ECO? like a tracking system?

 

[giggs11]

Yes, an example of a tool that can cater to ECO is Synopsys ECO.

 

[rol73]

To simplify an eventual ECO process, I'll suggest to ever insert some spare cells in any design... so the ECO could be a simple re-routing of your chip, and not a total re-synthesis...

 

[tom123]

The ECO is engineering chang order,

it's a action for fixing bug at the last minutes,

after synthesis, you should place some spare cells

in netlist for ECO use.

The best way is do design correct at the first time,

not to do ECO.

where does ECO fit in the whole ASIC design flow? what specific actions should we take for the ECO(e.g, reserver spare cells)?

 

[triquent]

anyone can talk what's the difference about eco, metal change and IPO? and which one cost less?

 

[johnz]

almost every company have a ECO flow, most of them have in-house tools to suport ECO.

 

[brianhe]

To speak simply, eco is just change the design on netlist. So that you did not need to make the change from the rtl level.

ECO is used normally for timing closure. After P&R, you may still have some timing issue, such as heavy load, small buffer... then you can manually replace the component. e.g. change the INVERTER with higer driving capability.
For small functional change, ECO can also be used. Normally, there are some spare cells in the netlist. So you just need change the wire connection.

Added after 10 minutes:

Normally we need not special ECO tool, for what we do is jsut manually modify the netlsit. But the net/wire name in may be very long, and it may corss several hierarchy.So it is eacy to make mistake.
nECO, a function of debussy(new name is Verdi, Novas Cop.) is a good tool to avoid such mistake.
PS, sometime you may need to replay lots of component, such as flip-flop, then you'd better write a script(with perl often) to do so.