How to divide the frequency by any value ?

[leongch]

frequency divide by 1.6

hi all,
I would like to know, anywhere which we can divide the frequency to what ever value we want? For example divide by 1.3, 1.25... 1.7, 1.8 , 5.2 ect...

any ideas??

regards,
chongleong

 

[Davood Amerion]

frequency divide by 1.6

use PLL and frequency divider

 

[echo47]

frequency divide by 1.6

If you are using a modern Xilinx FPGA, try the frequency synthesizer in the DCM block. For example, to divide a clock by 1.6, set CLKFX_MULTIPLY to 5 and CLKFX_DIVIDE to 8.

The DCM synthesizer is fine for some applications, but not all. Sometimes an external PLL is the right choice.