Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to distribute the internal pll clock source in fpga

Status
Not open for further replies.
Y

Youncen

Member level 2
Joined
Oct 30, 2005
Messages
50
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,637
how to distribute the internal pll clock source over the global clock network,
I mean in the quatus environment with cyclone

waiting and thanks for your reply
 

it is done automatically through the software. Even if you are using PLL. don't worry.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top