How to distinguish behavioral and structural in Verilog In

[letan]

structural behavior verilog

Hi!

I have file verilog in nestlist, and I don't know what it is? Behavioral or structural.

I just study verilog so I can't distinguish.

May anyone help me?

Thanks

 

[leongch]

behavioral structural verilog

If it is netlist, it should be structural

 

[imon]

verilog behavioral structural

can you post the verilog file? that's the only to be sure about

 

[semiconductorman]

verilog structural vs behavioral

It is not so much as a code but more with methodlogy but closly oberserving the code does give you a idea of what it is . If you have " wait " statements etc it is definetly behaviourly code.

 

[kishore2k4]

structural and behavioural verilog difference

IMHO, if it describes the behavior then its behavioral and if it describes the structure then its structural. Just try to make a mental image of the circuit that the HDL is describing. Keep in mind that when viewed as black box both the types are functionally equal, provided they are written that way.

 

[ravipati]

verilog behavioural vs structural

Instances will be in the stuctural .
procedures/always in the behavioral.
assaign in data flow.

 

[shiv_emf]

verilog behavioral and structural

well i think ! after synthesis u will get netlist which is obviously structural description of logical connections between standard cells

 

[sekapr]

behavioural vs structural verilog

behavioural describes the just data flow, structural describes the data flow with the components.

 

[jason99pan]

difference between behavioral and structural

If you just have a netlist file, I think it cannot be determined whether It is behavioral or structural. The reason is both HDL entry and schematic entry can generate netlist file.
If it is schematic entry, it will be structural.
If it is HDL entry, it cannot be determined whether it is behavioral or structural unless you see the details of the netlist file.
As I know, some netlist file will describe structural. Then maybe the design is structural.
If I am wrong, please correct me.

 

[bbgil]

structural vs behavioral verilog

one difference between structural and behavioral is that in behavioral, the use of assign and bitwise operators are common whereas in behavioral, relational and decison making operator are used (i.e. if then, elsif). ALso behavioral tends to focus on how output will be generated (flow) rather than how it is connected (structure/components). Behavioral gives the HDL used more flexibility in routing, plotting and mapping into target FPGA devices. hope this helps

 

[letan]

difference between behavioural and structural

Thanks, everybody

You are very kind

Thanks