How to distill the falling edge of an impulse?

[sunjiao3]

Hi, friends. I encountered a problem. There is a logic sigal DIS which will become an impulse by random. I wanna distill it's falling edge when this change occurs. Here, I used RS triggers. (I built them by nmos and pmos and simulated with hspice.)__master-slave RS trigger built on NAND gates which will sample the input on rising edge and output the change on falling edge and basic RS trigger built on Nor gates.
I set the 's' of RS trigger '0', and the signal DIS as the input of 'R'. Then, having passed 4 inverters, the delayed DIS is used as the input of clk. However, the Qp and Qn remained unchanged. Then, I made 2 signals, one of them is about 10us/100us delayed to compose the other signal. The output still remain unchanged. So, it seems that it not the delay time that causes such problem.
Friends, could any of one give me some suggestions? Both on plan and structure. Thank you very much!

 

[wwfhm2002]

Maybe I don't get your question, but according my understanding I give a basic solution:

input DIS
using a register to get the one clock cycle delayed signal DIS_D1
using a register to get the two clock cycle delayed signal DIS_D2

Then DIS_RESULT = !DIS_D1 & DIS_D2

If there is a falling edge of DIS, then there will be a active high pulse in signal DIS_RESULT


Note: this solution is only suitable in the case of clock frequency is twice more than falling edge occuring frequency.

 

[sunjiao3]

Well, thank you very much for your suggestion. But, there is some problem.
I avoid using delayer here since it will bring trouble. So, I will try to use the DIS signal itself as the clock of the RS trigger. Attention that the DIS is not a periodical signal. Thank you very much!