lhlbluesky
Banned
as we know, bandgap circuit has two stable operating points,so a start up circuit is needed;but i find that when i disable my start up circuit,and make vdd a fixed dc voltage, for example 1.8v for smic 0.18mm process, the output vref can still start up
after a longer time about 200ms;while i enable my circuit, the start up time is only 3ms or so;i guess the former appear because there is nonzero static leakage current in the circuit, so even if there is no strat up circuit, it can start up also after a long enough time,is that right?if not right , what is the correct case?
the other question, someone says the bandgap circuit needs a "dead point",that is the static stable operating point which appears for no start up circuit,i add nodeset for nmos bias transistor(gate=0) and pmos bias transistor(gate=vdd) to realize the "dead point"when i do my simulation, is that right? if not, how to design the "dead point" correctly?
pls give me some detailed advice,thanks all.
after a longer time about 200ms;while i enable my circuit, the start up time is only 3ms or so;i guess the former appear because there is nonzero static leakage current in the circuit, so even if there is no strat up circuit, it can start up also after a long enough time,is that right?if not right , what is the correct case?
the other question, someone says the bandgap circuit needs a "dead point",that is the static stable operating point which appears for no start up circuit,i add nodeset for nmos bias transistor(gate=0) and pmos bias transistor(gate=vdd) to realize the "dead point"when i do my simulation, is that right? if not, how to design the "dead point" correctly?
pls give me some detailed advice,thanks all.