Hi Wice,
I think this circuit will not give 50% duty cycle ....its duty cycle will depend on propagation delay of F/F , delay of XOR and not gates ....
If you are having any circuit which will give 50% duty cycle then post that one ....
Thanks in Advance ..
Regards
You could you xor gates to do the same provided you should have shifted version of I/P clk ? This ckt going to be pure combinational .
one I/P of XOR is direct clk
other I/P is T/4 shifted version of clk .
in this way you can generate multiply by two clk . This is almost 50% duty cycle .
But you should use special cells if you want to do this in SOC (delay should PVT invariant or should be impacted less) ...
Hi Wice,
I think this circuit will not give 50% duty cycle ....its duty cycle will depend on propagation delay of F/F , delay of XOR and not gates ....
If you are having any circuit which will give 50% duty cycle then post that one ....
Thanks in Advance ..
Regards
you can use this circuit 2 times, then the original input clock can be multiplied by 4 ,then use a ff to divide it by 2. you can get a 50% duty and multiplied clock at last.
Hi Wice ,
as I am thinking 50% duty cycle will not come ( because after multiplied by 2 ,when you will do again muliplied by 2 that times input is not 50 % ) , Please Try once urself with waveforms and if its possible then Please upload here ....
dont design any of the clock multiply circutes with the digital cells.since the duty cycle will vary depend on the load and the cell you can't expect a stable duty cycle clock from a digital circute.instred of that you may go for the analog PLL/(phase locked loops) which will genrate the stable clock which is multiple of the given clock with the required duty cycle(almost stable in all conditions).