How to design the circuit of clock multiplication?

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sora5563

Newbie level 6
multiplication waveforms circuit

Can any body help to provide the circuit that can perform
the waveform as shown in the figure above.
It is the clock multiplication![/img]

uditkumar1983

clock multiplication circuit

hi ,
i also wants to know above circuit ..except DLL/PLL.....

Regards

wice

Member level 1
sora5563 said:

Can any body help to provide the circuit that can perform
the waveform as shown in the figure above.
It is the clock multiplication![/img]
hi ,you can hav a look at this circuit.

wice

Member level 1
timing sequence diagram.
Tnot denotes delay made by not gate
Txor denotes delay nade by xor gate

sora5563

Newbie level 6
Thank you very much!!!

rsrinivas

the above works but to obtaain 50 % duty cycle is not easy. it's also shown in the diagram.
however functional simulations are fine

uditkumar1983

Hi Wice,
I think this circuit will not give 50% duty cycle ....its duty cycle will depend on propagation delay of F/F , delay of XOR and not gates ....
If you are having any circuit which will give 50% duty cycle then post that one ....
Regards

yln2k2

Member level 5
Hi ,

You could you xor gates to do the same provided you should have shifted version of I/P clk ? This ckt going to be pure combinational .

one I/P of XOR is direct clk
other I/P is T/4 shifted version of clk .
in this way you can generate multiply by two clk . This is almost 50% duty cycle .
But you should use special cells if you want to do this in SOC (delay should PVT invariant or should be impacted less) ...

Thanks & Regards
yln

uditkumar1983

Hi Yln2k2,
as you are telling its same like DLL ....In DLL also its will multiply the frequency using shifting the clk.... or something different....

And you required to know whats frequency i m going to use for getting shifted T/4 .....

Regards

wice

Member level 1
uditkumar1983 said:
Hi Wice,
I think this circuit will not give 50% duty cycle ....its duty cycle will depend on propagation delay of F/F , delay of XOR and not gates ....
If you are having any circuit which will give 50% duty cycle then post that one ....
Regards
got a 50% duty is not difficult.

you can use this circuit 2 times, then the original input clock can be multiplied by 4 ,then use a ff to divide it by 2. you can get a 50% duty and multiplied clock at last.

uditkumar1983

Hi Wice ,
as I am thinking 50% duty cycle will not come ( because after multiplied by 2 ,when you will do again muliplied by 2 that times input is not 50 % ) , Please Try once urself with waveforms and if its possible then Please upload here ....

Regards

rameshsuthapalli

Full Member level 3
Hi,

dont design any of the clock multiply circutes with the digital cells.since the duty cycle will vary depend on the load and the cell you can't expect a stable duty cycle clock from a digital circute.instred of that you may go for the analog PLL/(phase locked loops) which will genrate the stable clock which is multiple of the given clock with the required duty cycle(almost stable in all conditions).

regards,
ramesh.s

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