How to design outpubuffer in 8GHz divider by2
Hi,
1.This divider's deisgn is based on 0.18um Mixed Signal/RF CMOS.
2. The divider is based on D filp-flop,realized using CML(current mode logic). and its input and output are differnential.
3. This figure is output buffer schematic from a paper, it is used to create sufficient output voltage swing, it consists a source follower and two amplifier stage
But I doubt its bandwidth and stability, please help to check it.
.