andy2000a
Advanced Member level 2
current regulator
some LDO asic only work on < 10ua ..
how to design it ? regulator need OPA + bandgap ..
if bandgap total working current < 1u ,
cmos process design use BJT model (parasic device) can be use under
such small current ( maybe BJT current < 100na ) ??
I don't think FAB have good spice model for BJT device ..
some LDO asic only work on < 10ua ..
how to design it ? regulator need OPA + bandgap ..
if bandgap total working current < 1u ,
cmos process design use BJT model (parasic device) can be use under
such small current ( maybe BJT current < 100na ) ??
I don't think FAB have good spice model for BJT device ..