How to design a SRAM cell using Spice and incorporate it in Verilog code?

[arup172]

For synthesising a cache memory, I need SRAM cells. If i describe them using verilog, how do I incorporate the sense amplifiers. Is there any other way by which i can design a SRAM cell using Spice and incorporate it in my verilog code.

The cache controller and memory design has been done using Verilog but memory cells have been declared as registers which need to be replaced with actual SRAM cells.

Can anyone help with any ideas??

 

[koggestone]

Re: Cache Memory Design

SRAMs are NOT synthesizable.

SRAMS are custom designed and instantiated as Macros in RTL and during Synthesis.

 

[arup172]

Re: Cache Memory Design

By custom design you mean a transistyor level schematic? If I do that how do I instantiate that into my verilog code?

 

[ajhunt18]

I have the same problem but I am facing these problems in translating analog circuits to digital. Like the Access Transistors in the SRAM Cell, I don't know what's it's corresponding component in digital.