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How to design a low jitter clock generation circuit

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Junior Member level 1
Sep 21, 2015
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I want to do a project about low jitter clock generation for SOC or ADC use.The main idea is to do PLL. Is there any suitable structure for low jitter performance? For example,can Sigma-Delta work for this particular use? In addition, the PLL is based on ring VCO for we use CMOS digital process,is ring VCO ok?

Thanks for all the advice.

For lowest jitter (phase noise) you need to have an oscillator that is tuned with a very high Q resonant circuit. Best would be a crystal or surface acoustic resonator for fixed frequency, or at the very least an LC resonant tank circuit if you need to vary the frequency.

The amplifying device associated with the oscillator must also be of a low noise type.

Ring oscillators, and various types of multivibrators using C and R as timing elements are just horrible for jitter. These trigger on slowly rising or falling voltages, and any thermal noise will interfere with the timing interval, and create jitter.
A ring oscillator contains a whole bunch of these horrors, so its definitely not a preferred solution.

Best bet would probably be to buy a commercial VCO that will have a specification for phase noise and jitter if its just for a one off project.

If you plan to build it yourself, it would take a great deal of testing to equal a good off the shelf product.

If you want to a low jitter PLL, you should use LC structure. You focus on designing oscillator and after, you optimize phase frequency detector.

But in recent IC technologies, Inductor is not used because of it is large size. so is there anyway we can achieve low jitter without LC oscillators?

Is there any good Delay concepts for low jitter?


Recently,I've found some delay structures for low jitter use. For example, positive feedback or latch to speed up the voltage rising or falling, full swing without tail current source and ......

This is for improving VCO jitter performance, but I want to konw if there is any system level structure for low jitter?

Thanks, hoping for more advice

Time delays using R and C are noisy and jitter.
A a high Q resonance is required, something that peaks at one exact resonant frequency very sharply.

Thank you.
As I know, LC oscillator is good,but mainly for communication IC circuit. If I design a PLL for system clock, is this enough with ring VCO? If it's enough, how can I get better jitter performance for further improvment.


As you know, LC structure has lower phase noise than other structure but inductor is difficult in integrating on IC. If you don't want to use LC, you can design DIFFERENCE ring oscillator. I see that on the IEEE explore, there are a lot of papers about it.

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