incoming sine wave is already digitized. To track it, I intend to use a all-digital PLL, which consists of a phase comparator(a multiplier), a loop filter and a NCO.
Earlier I was confused with the concept "equal steps", or "fixed phase increment". Now I see it's not necessarily a fixed phase increment --- the phase increment could vary so that NCO could catch up with the incoming digitized sine wave.
Using LUT, the address corresponds to the frequency... so adding 1 each system clock generates a sine wave with the frequency of "system frequency / 2^N", adding 2 each system clock merely doubles the generated sine wave frequency.
The more accumulator word widths we use, the finer the frequency becomes. But there could always be some residual frequency error left, due to the fact that LUT address only accepts integer increment.
That's how I understand it...correct me if anything is wrong...thanks.