Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to design a CMOS bi-phase clock generator?

Status
Not open for further replies.

chihwt2003

Newbie level 6
Joined
Jul 7, 2005
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,399
CMOS bi-phase clock

Hi all,

Does anyone knows how to design a CMOS bi-phase complement clock generator which have a minimum delay at the output??? Thanks in advance.
 

gevy

Full Member level 6
Joined
Nov 17, 2004
Messages
340
Helped
60
Reputation
120
Reaction score
29
Trophy points
1,308
Location
Russia
Activity points
2,167
Re: CMOS bi-phase clock

Usually I apply bi-phase nonoverlaping clock on basis on RS-Flip-Flop with delay elements.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top