how to design a 3 bit binary shift register

[moonnightingale]

I want to design a 3 bit binary shift register with parallel load facility. A control line Load/shift when asserted high loads external parallel inputs and when low causes shift right. Can u give me logic diagram of above stated register by using 2 D Flip Flops and 2-1 multiplexers.
Thanks

 

[qieda]

https://obrazki.elektroda.pl/40_1291980076.jpg

 

[moonnightingale]

can u kindly explain this tome

 

[mrflibble]

What specific part do you not understand?

 

[moonnightingale]

I want to design a 3 bit binary shift register with parallel load facility. A control line Load/shift when asserted high loads external parallel inputs and when low causes shift right. Can u give me logic diagram of above stated register by using D Flip Flops and 2-1 multiplexers.
Thanks

iN UPPER question i wrote 2 Flip flops by mistake
dont u think that there should be three D FLIP FLOPS FOR THREE BIT

 

[mrflibble]

What do you think?

 

[lostinxlation]

Homework ?

We can't be more clearer than the pic in the post #2.

 

[moonnightingale]

Its not a homework, u can reply to this thread after one week as well.
I will still be happy to learn it
What i think there should be three D Flip Flops

 

[qieda]

Hi,

maybe we have a misunderstanding.
What do you think a "3 bit binary shift register" should do?
For my understanding see next picture and some words.

(I added a third FF at the output, this has no influence on the principal functionality)

see
https://obrazki.elektroda.pl/99_1292225787.jpg

At time T0 the rising edge of the clock latches the 3bit data "ABC" into the 3 FF's X0,X1 and X2
This is because the load signal is high and the multiplexer select the din data as an input to the FF's

So after this clock edge (T0) we have the data C at the output of X0, B at the output of X1 and A at the output of X2 which is similar to dout.
With the next rising clock edge (T1) the multiplexer are now select the output of the previous FF as an input. So after this clock edge we have C at the output of X1 and B at the output of X2 which is similar to dout.
With the final clock edge (T2) we now shift C to the output of X2 which is dout.

With T3 you can load the next parallel data input and it is shifted again.

regards