Hi,
Thanks a lot.
I think that your proposal will work for me in case of clk_sel=1. I will just try it.
One thing shall be clarified: In my design, PLL is used to double the clock frequency.
When clk_sel=0, the CLK0 is a 64MHz clock and used as system clock directly,
when clk_sel=1, the CLK0 is a 32MHz clock and translated to 64MHz by PLL, then used as system clock.
Still, I am wonder why it is PLL output pin, instead of MUX output pin,
that shall be used as root of CTS.
As you know, in case of clk_sel=0, PLL output pin is not used anyway!
And also in your proposal,why is there no need of "set_case_analysis 0"?
Best regards