Jan 27, 2006 #1 A alexz Full Member level 5 Joined Nov 19, 2004 Messages 283 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location UK Activity points 2,246 Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); define mybit myport(0) ; now I would use "mybit" instead of myport(0) . Also, what is the way to do that with literal numbers? define aaa 15 or define bbb '1'
Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); define mybit myport(0) ; now I would use "mybit" instead of myport(0) . Also, what is the way to do that with literal numbers? define aaa 15 or define bbb '1'
Jan 27, 2006 #2 K keano Member level 1 Joined Dec 24, 2004 Messages 36 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Location TUNISIA Activity points 251 Re: VHDL basics question alexz said: Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); define mybit myport(0) ; now I would use "mybit" instead of myport(0) . Click to expand... Well I looked in all my VHDL books and I couldn't find a way to do it. Personally, I think it's not possible but I may be wrong. alexz said: Also, what is the way to do that with literal numbers? define aaa 15 or define bbb '1' Click to expand... You may use constants: constant aaa : integer := 15; constant bbb : std_logic := '1'; LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT ( d0, d1, s: IN STD_LOGIC; y: OUT STD_LOGIC); END multiplexer; ARCHITECTURE Behavioral OF multiplexer IS constant aaa : std_logic := '0'; BEGIN y <= d0 WHEN s = aaa ELSE d1; END Behavioral;
Re: VHDL basics question alexz said: Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); define mybit myport(0) ; now I would use "mybit" instead of myport(0) . Click to expand... Well I looked in all my VHDL books and I couldn't find a way to do it. Personally, I think it's not possible but I may be wrong. alexz said: Also, what is the way to do that with literal numbers? define aaa 15 or define bbb '1' Click to expand... You may use constants: constant aaa : integer := 15; constant bbb : std_logic := '1'; LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT ( d0, d1, s: IN STD_LOGIC; y: OUT STD_LOGIC); END multiplexer; ARCHITECTURE Behavioral OF multiplexer IS constant aaa : std_logic := '0'; BEGIN y <= d0 WHEN s = aaa ELSE d1; END Behavioral;
Jan 27, 2006 #3 K kumar_eee Advanced Member level 3 Joined Sep 22, 2004 Messages 814 Helped 139 Reputation 276 Reaction score 113 Trophy points 1,323 Location Bangalore,India Activity points 4,677 Re: VHDL basics question I think u can't define a single bit from ur port declaration.... For literal nmbrs, u can use constants.... which is similar to Parameter in Verilogeg Eg: constant unit_delay : Time := 1 ns;
Re: VHDL basics question I think u can't define a single bit from ur port declaration.... For literal nmbrs, u can use constants.... which is similar to Parameter in Verilogeg Eg: constant unit_delay : Time := 1 ns;
Jan 27, 2006 #4 A alexz Full Member level 5 Joined Nov 19, 2004 Messages 283 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location UK Activity points 2,246 Re: VHDL basics question I think I have found a way of doing it... That is ALIAS SIGNAL myarray : std_logic_vector(31 downto 0); ALIAS mybit : std_logic is CANdataIn(0); mybit can be used as the LSB bit of myarray
Re: VHDL basics question I think I have found a way of doing it... That is ALIAS SIGNAL myarray : std_logic_vector(31 downto 0); ALIAS mybit : std_logic is CANdataIn(0); mybit can be used as the LSB bit of myarray
Feb 8, 2006 #5 N nee_naresh04 Member level 2 Joined Dec 15, 2005 Messages 47 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,657 Re: VHDL basics question Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); yes i think its possible when u define like myport : inout std_logic_vector( 0 downto 0); because in case of xilinx cad tool we can specify like this...
Re: VHDL basics question Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); yes i think its possible when u define like myport : inout std_logic_vector( 0 downto 0); because in case of xilinx cad tool we can specify like this...
Feb 8, 2006 #6 A alexz Full Member level 5 Joined Nov 19, 2004 Messages 283 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location UK Activity points 2,246 Re: VHDL basics question nee_naresh04 said: Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); yes i think its possible when u define like myport : inout std_logic_vector( 0 downto 0); because in case of xilinx cad tool we can specify like this... Click to expand... What is the point?
Re: VHDL basics question nee_naresh04 said: Is there a way to define a one bit from an std_logic_vector? something like that: myport : inout std_logic_vector(15 downto 0); yes i think its possible when u define like myport : inout std_logic_vector( 0 downto 0); because in case of xilinx cad tool we can specify like this... Click to expand... What is the point?
Feb 8, 2006 #7 N nee_naresh04 Member level 2 Joined Dec 15, 2005 Messages 47 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,657 Re: VHDL basics question myport : inout std_logic_vector(0 downto 0); i think the above declaration may be used..just check it once..i am not confident...
Re: VHDL basics question myport : inout std_logic_vector(0 downto 0); i think the above declaration may be used..just check it once..i am not confident...