How to define a one bit from an std_logic_vector?

[alexz]

Is there a way to define a one bit from an std_logic_vector?

something like that:

myport : inout std_logic_vector(15 downto 0);

define mybit myport(0) ;

now I would use "mybit" instead of myport(0) .

Also, what is the way to do that with literal numbers?
define aaa 15
or
define bbb '1'

 

[keano]

Re: VHDL basics question

Is there a way to define a one bit from an std_logic_vector?

something like that:

myport : inout std_logic_vector(15 downto 0);

define mybit myport(0) ;

now I would use "mybit" instead of myport(0) .

Well I looked in all my VHDL books and I couldn't find a way to do it. Personally, I think it's not possible but I may be wrong.

Also, what is the way to do that with literal numbers?
define aaa 15
or
define bbb '1'

You may use constants:

constant aaa : integer := 15;
constant bbb : std_logic := '1';


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY multiplexer IS PORT (
d0, d1, s: IN STD_LOGIC;
y: OUT STD_LOGIC);
END multiplexer;

ARCHITECTURE Behavioral OF multiplexer IS

constant aaa : std_logic := '0';

BEGIN

y <= d0 WHEN s = aaa ELSE d1;

END Behavioral;

 

[kumar_eee]

Re: VHDL basics question

I think u can't define a single bit from ur port declaration....


For literal nmbrs, u can use constants.... which is similar to Parameter in Verilogeg

Eg:
constant unit_delay : Time := 1 ns;

 

[alexz]

Re: VHDL basics question

I think I have found a way of doing it...

That is ALIAS

SIGNAL myarray : std_logic_vector(31 downto 0);
ALIAS mybit : std_logic is CANdataIn(0);


mybit can be used as the LSB bit of myarray

 

[nee_naresh04]

Re: VHDL basics question

Is there a way to define a one bit from an std_logic_vector?

something like that:

myport : inout std_logic_vector(15 downto 0);

yes i think its possible when u define like

myport : inout std_logic_vector( 0 downto 0);

because in case of xilinx cad tool we can specify like this...

 

[alexz]

Re: VHDL basics question

Is there a way to define a one bit from an std_logic_vector?

something like that:

myport : inout std_logic_vector(15 downto 0);

yes i think its possible when u define like

myport : inout std_logic_vector( 0 downto 0);

because in case of xilinx cad tool we can specify like this...

What is the point?

 

[nee_naresh04]

Re: VHDL basics question

myport : inout std_logic_vector(0 downto 0);

i think the above declaration may be used..just check it once..i am not confident...