How to decrease the area of net in DC?

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HI, I just learn to use DC to do the layout for my RTL digital circuits recently, but I find the area of net in reports is really large. Is there some hint to decrease it?
 

Do u choose right wire load model? Net area is just a rough estimation. ....
 

entropy said:
Do u choose right wire load model? Net area is just a rough estimation. ....
Click to expand...

yes, the wire load model has been specified in constrain.tcl, the screenshot below shows a lot of area for wire.
 

U mean GUI portion occupies too much in the schematic ? Is this an issue to worry about?
 

entropy said:
U mean GUI portion occupies too much in the schematic ? Is this an issue to worry about?
Click to expand...

No, I means the wiring area, connecting gates and registers, just wondering why it's so large
 

It's just for drawing aim. It is not the real net area. If u want to check net area, you need to use command report_area.
 

entropy said:
It's just for drawing aim. It is not the real net area. If u want to check net area, you need to use command report_area.
Click to expand...

Combinational area: 5408.723633
Noncombinational area: 1683.158447
Net Interconnect area: 52920.265625

seems the Net Interconnect area is nearly 10 times Combinational area, is it normal?
 

i did't get ur words,, using DC for layout
 

raju3295 said:
i did't get ur words,, using DC for layout
Click to expand...

I have find ways to get my design optimized, but thank u anyway~~
 

Could you please share it with us?
Thanks.
 

Syswip said:
Could you please share it with us?
Thanks.
Click to expand...

well, I just intergrate the similar conbination logic into one logic and reduce the Combinational area, so the Net Interconnect area decrease. I don't know if I say it clearly. For instance,I implement logic in different 'case', now all of them can be intergrated into one.
 

As I understand you only optimized your design. You didn't do any DC tricks.
Did you?

Bests,
Syswip
http://syswip.com
 

Syswip said:
As I understand you only optimized your design. You didn't do any DC tricks.
Did you?

Bests,
Syswip
http://syswip.com
Click to expand...

yeah, I'm just a beginner, so what I can do is now limited to the optimization of the algorithm and the RTL level.
 

I don't think you should read too much on what DC reports as interconnect area. This number is largely exaggerated and not correct. If you want a better estimate of the wire area, you should get it from ASTRO or IC Compiler. I have many times got ridiculously large interconnect numbers from DC and a completely smaller number from their layout tools. So, I say ignore DC when it comes to interconnect estimates.
 

DC Topographical also will give quite realistic results.
 

just care the "Total cell area", in front-end. (if you use wire-load model flow)
 

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