hltll
Junior Member level 1
I am designing a charge pump for PLL.
The structure is similar to traditional one which is: cascode pmos as up current, cascode nmos as down current, the middle is switch. The output voltage is from 0.4V to 1.4V as VDD=1.8V. If I want to get the DC current mismatch( (Iup-Idn)/[(Iup+Idn)/2]) less than 1% at output voltage from 0.4 to 1.4V, the switch PMOS/NMOS should be very big(10u/180n) to get small VDS. However if the switch PMOS/NMOS is very big, in tran-simulation the current jitter is very big, this will cause |Iup-Idn| too large during UP and down current is both on. If I decrease the w/l of the switch to less than 1u/180n, the |Iup-Idn| during tran simulation will be small, but the DC mismatch will be large.
My problem is as follow:
1. When we design a charge pump in PLL, which specs should be consider?
2. If the current mismatch is one spec, is that mean dc current mismatch or tran current mismatch
3. When we design a pll, the current of the cp is less than 100u or 100u~1mA, which range should we select to get good close-in noise of pll.
Looking forward your reply
The structure is similar to traditional one which is: cascode pmos as up current, cascode nmos as down current, the middle is switch. The output voltage is from 0.4V to 1.4V as VDD=1.8V. If I want to get the DC current mismatch( (Iup-Idn)/[(Iup+Idn)/2]) less than 1% at output voltage from 0.4 to 1.4V, the switch PMOS/NMOS should be very big(10u/180n) to get small VDS. However if the switch PMOS/NMOS is very big, in tran-simulation the current jitter is very big, this will cause |Iup-Idn| too large during UP and down current is both on. If I decrease the w/l of the switch to less than 1u/180n, the |Iup-Idn| during tran simulation will be small, but the DC mismatch will be large.
My problem is as follow:
1. When we design a charge pump in PLL, which specs should be consider?
2. If the current mismatch is one spec, is that mean dc current mismatch or tran current mismatch
3. When we design a pll, the current of the cp is less than 100u or 100u~1mA, which range should we select to get good close-in noise of pll.
Looking forward your reply