Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to decrease Charge Injection Error in Switches......

Status
Not open for further replies.

shady205

Full Member level 2
Joined
Oct 1, 2006
Messages
120
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,296
Location
India Bangalore
Activity points
2,058
Hello Friends..

How to decrease Charge Injection Error in Switches......

We basically know that we can reduce using dummy transistors...

Is there any efficient way to still reduce the effect...

awaiting for your Reply's

Thanks & Best Regards

Shady205
 

The other not so efficient method is to greatly reduce the impedance on the driving side of the switch so that the charge distribution is unequal (more towards the low impedance node).
 

The clock that controls a switch connecting to the gnd(or CM voltage level) goes down a little bit earlier that the other, that often used in the SC circuit.
 

safwatonline said:
bottom plate sampling
Yes. Here's a short explanation:
 

Attachments

  • bottom-plate-sampling_1291.pdf
    48.9 KB · Views: 105

    shady205

    Points: 2
    Helpful Answer Positive Rating
BackerShu said:
The clock that controls a switch connecting to the gnd(or CM voltage level) goes down a little bit earlier that the other, that often used in the SC circuit.

good and Bottom plate sampling is also can reduce it.

Added after 3 minutes:

erikl said:
safwatonline said:
bottom plate sampling
Yes. Here's a short explanation:

thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top