How to decide the different Read/Write commands for PCI ?

[CRiSP]

a PCI preoblem

how to deceide the different Read/Write cmd (Memory Read、Memory Read Line、Memory Read Multiple及Memory Write、Memory Write and Invalidate) when PCI master initiates one transaction by DMA of Backend Logic?

 

[xv_ning999]

a PCI preoblem

In what part decide would be made? The pci master ?or target device ?

 

[CRiSP]

Re: a PCI preoblem

In what part decide would be made? The pci master ?or target device ?

pci master

 

[hung81]

a PCI preoblem

you can find if in here:
www.singlix.org/trdos/PCI22.pdf

 

[andonie12]

Re: a PCI preoblem

CRiSP,

If the PCI sending you one signal called: backend_rdn_wr in this case you have to build a state machine to generate the write_enable and read_enable signals to provide to the flash. Below is part of my design on how to generate the write/read signals based on one PCI signal backend_rdn_wr. Let me know if you need more help on this topic

case flash_state is

when IDLE => -- present valid address,data
flash_cen_int <= '0'; -- and chip enable here
flash_state <= WE1;
when WE1 => -- drive wen +30 nsec
flash_wen_int <= not backend_rdn_wr;
flash_oen_int <= backend_rdn_wr;
flash_state <= WE2;
when WE2 =>
flash_state <= WE3;
when WE3 =>
flash_state <= WE4;
when WE4 => -- latch data + 120 nsec
flash_reg <= flash_data_c;
flash_wen_int <= '1';
flash_oen_int <= '1';
flash_state <= WE5;
when WE5 => -- lift cen +150 nsec and signal
flash_cen_int <= '1'; -- o_backend_rdy to the pci backend
flash_state <= DONE;
when others => null;

end case;

 

[abhineet22]

a PCI preoblem

obiously pci master

 

[Prasanna Kumar]

Re: a PCI preoblem

I beleive we have C/BE command with 4 bit value which defines the each of the above transactions where the slave interface has to look and understand,

 

[eelinker]

Re: a PCI preoblem

Try this book:
PCI system architecture
BY: Tom Shanley