How to decide opa spec when you design a ADC ?

[mpig09]

Dear all :

I will design a 10-bit ADC, the following description is me spec :
1.VDD:3.3V
2.Vref : 1.65V
3.Input voltage range : +/- 1V
4.Input max. speed : hundred KHz.

I will use pipeline or cyclic type adc for this design, could you
give me some suggests to decide the opa spec ?
(gain, bandwidth, ...)


Thanks for your help.

mpig

 

[hr_rezaee]

hi
for pipeline adc see Abo thesis.
google it.
regards

 

[sutapanaki]

From your LSB size you can determine the accuracy that you need your opamp to settle to. The output voltage should be within +- 0.5LSB. This in turn defines your minimum opamp gain.
From your clock and this is true especially for the sample and hold you can determine how much time you have for your opamp to settle. That is, you have so many timeconstants to settle to the required accuracy (% of the final value) for the time of half a clock period. Then, your loop gain unity gain frequency is the reverse of the timeconstant.