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How to decide clock synthesis parameters such as latency and skew?

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lightcloud

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I want to know how to decide clock synthesis parameter
such as latency,and skew,
Is there any experience expressions?
 

zyphor

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Re: question about cts

it is determined by you register number. if one stage clock buffer can drive 12 clock buffer node, you can computer how many stages it needs to drive the registers in your design.
 

leeenghan

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Re: question about cts

Hi,

Skew is in a way decided by the process technology you are using, and the methodology you want to use for timing closure. It may be also dependent on the design and the floor plan. For 0.13um to 0.18um, 250ps should be reasonable.

A smaller skew will give a slightly larger latency. In general, the tool will build a tree with the smallest latency it can achieve. Thus, if the tool achieve a latency of 3ns, it deos not matter if you set a max of 4ns or 5ns. Most of the time even if you set a value less than 3ns, you will still get a value of around 3ns but wilth worst skew and more clock buffer inserted.

One approach is to use a relaxed skew and latency target. Note now the quality of the clock tree (skew,latency, number of buffer level, number of buffer...etc) and then tighten it without a significant drop in the quality.

Regards,
Eng Han
 

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