Thanks for your reply.
Actually it is the 2nd rev of chip, there are warnings of timing violation during simulation, but only one mismatch.
we ignored the warnings because when we did 1st rev, there were also many warnings of timing violation but no mismatch, and it got pass on ATE test).
now, i have got the scan cell (FF), and ploted its waveform during unloading. it looks ok (no x state, and having enough margin).
i also ploted the waveform during "caputure"... but the combinational logic circuits connecting with that FF is so deep and complex, i don't know whether and how to trace them...
i also tried to reduce the scan clock down to one tenth, but still failed at the same scan cell and pattern.
is there any method for that, please?