How to deal with IO and Core with diff supply voltage?

[bailibl]

In my design,
Core DC supply voltage:1.8V
I/O DC supply voltage: 3.3V

My IO and Core power pad in the reference library is:
IO power pad cell：PLVDDH
IO ground pad cell: PLVSSH
Core power pad cell: PLVDDC
Core ground pad cell: PLVSSC

and I want to:
connect Core power pad to global net VDD
connect Core ground pad to global net GND
connect IO power pad to global net VDDH
connect IO ground pad to global net VSSH

and I want toin "Netlist In" ---> "Verilog In" command)
assign logic 1'b0:GND
assign logic 1'b1:VDD

1.What should I do when run "Verilog In", "EXP netlist"?
2.When "EXP netlist",in "global options" form,should I add global net "VDD" "GND"
for Core power and "VDDH" "VSSH" for I/O power??

 

[kgeorge123]

Yes you will have to tie the power cells /PADs to VDDH and VSSH which is you are saying for IO power. Basically you will have seperate ports on your topmost level entity where you will be getting this IO Power. Then later in RTL you will have to tie the IO cells to this port/net..

 

[lnc]

Yes ! I am using Magma . I have a same problem with you ! The Global power : vddd and gndd ( for digital part of the design) And Local power : avdd and agnd ( for analog part ) . There is a problem that both of power-structure connected by only one-pad ( it have 4 pad-pin : VDD , VSS and VDDIO , VSSIO ) . But in netlist , there's only connected VDD and VSS to net : vddd and gndd . two pin VDDIO and VSSIO not connect any net ... The End , when I asked my customer about it , They said they connect them later !
About you this problem ?

 

[wkong_zhu]

In Astro, you must add all power net (VCC,GND, AGND, AVCC, refer to your standard cell, Power net name are different in different library ) manually. In netlist, there are no power nets.