how to deal with errors caused by dummy transistors when LVS

[nige]

when I finished my LVS and see *.lvs report file, I found the dummy transistors usually causes some errors, and reports show the layout and schematic unmatched. I know these errors were not important, but affirming these errors also took me a lot of time. are there any good methods to deal with this problem?

by the way, I found after layout reduce, Dracula recognize some MOSFET as "PDW,SUP,PUP" and even "INV" in the *.lvs report. I didn't find any INV in the site *.lvs told me except a single MOSFET. what are "PDW,SUP,PUP"?Is there anybody can help me?

ps:I'm using Dracula and virtuoso to design a full-custom analog layout.

thank you!!!

 

[Fom]

Re: how to deal with errors caused by dummy transistors when

I know 2 ways.
First: insert all your dummy in schematic.
Second: use dummy layer to eliminate dummy structures from layout.
I prefer fist one. Because these structures actually exist in your design and it doesn't hurt to run postlayout simulation with these dummies. Sometimes you can catch real error.
About PDW, SUP and so on.

Parallel pullDoWn
Serial pullUP

So first letter S or P shows what kind of structure: serial or parallel.
Secon two letter show where the structure is connected: to Power or to Ground.

 

[sunjiao3]

Re: how to deal with errors caused by dummy transistors when

I don't know your case very well. But, as for me, when I do LVS using Dracula, I found no error from the report. I just conneted the two ends of the dummy resistor togerther to the VDD or GND without drawing them in the schematic, and there is no error. For the transistor, I havn't layout any dummy transistor on it, so I am not so sure.
Thanks fom very much for his clear explanation of SUP and PDW.

 

[Hughes]

If you can connect all terminals of a dummy transistor to one net, it can be pruned before comparison. Another way is to modify the LVS rule. For exampe, if all dummy mosfets haven't s/d diffusion contacts, you can exclude these devices before device recognition.

 

[Vamsi Mocherla]

the problem here is that the LVS should filter the devices which are connected as dummies. Please paster the following command in your rule deck for eliminating dummies.

FILTER-LAY-OPT = options...

where options are B,BA,C,D,E,F,H,I,J,K,L,M,N,O,P.

The options are for eliminating dummies where gates are connected to gnd, where sources and drains are connected together, where sources and drains are connected to gnd or to power supplies and so on.

I hope that this helps

 

[nige]

thanks for all your help. now I have used "FILTER-LAY-OPT " to eliminate the errors successfully.
at the same time, I think the suggestion of "insert all your dummy in schematic" is very good but needs more time , I will use this method in the future.

Added after 19 minutes:

another question to fom: what's the "SMID"?
where can I found the explaination of these abbreviation?

thank you

 

[piao]

Re: how to deal with errors caused by dummy transistors when

2 methods:

1. add dummy into your circuit;

2. update your LVS rule file, using a dummy layer to block out the dummy you do not want in your layout, then the dummys will not show in the extracted netlist.

I do not think using the option "FILTER-LAY-OPT" is a good choice.

 

[sambireddy]

one good way to eliminate the dummy trans lvs error is to add the dummys in the schematic.

 

[Fom]

Re: how to deal with errors caused by dummy transistors when

SMID is serial connection like SUP or SDW, but instead of VDD or GND it is connected to internal nodes.
All these definitions are described in Dracula Reference Manual.

 

[soorajsram]

Re: how to deal with errors caused by dummy transistors when

If you are using Dracula, the work is easy. There is an option to delete
the cell from the current layout gds for the DRC as well as LVS. It just
omit the cells you mention in the Dracula run setup.