How to create wire_load_model?

[wllee]

Hi, every body:
Does anyone know how to create wire load model? what kind of tools can generate?
Thanks

wllee

 

[windflower]

$ynop$y$ DC can do it.see $old please.

 

[kfy]

If you want to get a 'more' accuracy result in wire-load, you must have the layout database. Although the wire-load is not accuracy.

You can use "Planet" of Avant! (Synopsys) or "SPC" (cadence) or "PC" (Synopsys).

Check it ~

 

[msdnge]

As designers , we just create CWLM(Customer WLM) for our own chips. WLMs are created by Library vendors. When using CWLM/WLM , we are supposed to use the methdology of Link-to-Layout, so we can use PrimeTime with the SPEF from StarRC ( this one is accurate) or P&R tools . In VDSM, we are apt to use physical sythesis or physical knowledge based sythesis methdology, tools like Physical compiler (Synopsys) or First Encounter( Cadence) , but they needn't CWLM anymore.

 

[mediative]

In soc encounter environment, first extract parasitics based on Route. then generat a Wire Load Model
1. To generate wire load models, select
Timing—Generate Wireload Model.