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As designers , we just create CWLM(Customer WLM) for our own chips. WLMs are created by Library vendors. When using CWLM/WLM , we are supposed to use the methdology of Link-to-Layout, so we can use PrimeTime with the SPEF from StarRC ( this one is accurate) or P&R tools . In VDSM, we are apt to use physical sythesis or physical knowledge based sythesis methdology, tools like Physical compiler (Synopsys) or First Encounter( Cadence) , but they needn't CWLM anymore.