How to create Verilog test bench in Modelsim?

Thread starter ruwan2
Start date Aug 14, 2015

Status: Not open for further replies.

Aug 14, 2015

ruwan2

Member level 5

Hi,

I am new to Modelsim. I find there is a test bench template, but I don't find how to create it. Please see the picture. No matter what I add to the
'Design Unit Name', the 'Next' tab never turns to black.

The small Verilog module has compiled successfully.

Could you tell me how to create a test bench using the wizard for Verilog code?

Thanks,

Status: Not open for further replies.

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How to create Verilog test bench in Modelsim?

ruwan2

Member level 5

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