The uC SPI SCLK is 20MHz. The FPGA clock is 33MHz. I don't think I can sample the SCLK continuosly and then generate signals that detect rising and falling edge of SCLK and expect reliable operation since the FPGA system clock is not 4 times or more than the SCLK. Another issue is that the SCLK is not free running. It only toggles a few times when data is being transmitted.
Ach, you're right. That's what happens when I post too early in the morning.Sounds like a 1-bit wide FIFO. But how does it keep the frame information?
I was assuming a SPI receiver register and a word-wide FIFO.
What if to use a different input-output clock and width ratio? 1-bit input, but 8 bit output FIFO with output clock 1/8 of the input clk?Sounds like a 1-bit wide FIFO. But how does it keep the frame information?
I was assuming a SPI receiver register and a word-wide FIFO.
That means you have to use a serial-to-parallel shift register, shift in 8 data, write to FIFO. See post #2What if to use a different input-output clock and width ratio? 1-bit input, but 8 bit output FIFO with output clock 1/8 of the input clk?
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