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How to create a high speed FPGA SPI slave where SCLK cannot be sampled?

matrixofdynamism

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I need to design an SPI slave peripheral inside an FPGA that shall be used to communicate with a Microcontroller and configure the behaviour of the FPGA design. The SCLK and FPGA system clock frequency is close in range. This means that I cannot sample the SCLK continuously and use that to decide when to sample and shift the data from the SPI master. I have a few questions.
  1. If the SCLK input clock is almost of same order as the FPGA system clock? Does the clock signal connect directly into the FPGA registers? (b) If not then what is the alternative? I am in this situation where the FPGA system clock is not 4 times or more than the SCLK frequency.
  2. If (a) above is true then how do we write the timing constraints?
  3. The SCLK does not need to use global clock routing. Does this mean that any FPGA pin can be used for it?
How should such a slave be designed, and timing constrained and work in reliable way i.e all data is correctly transmitted into the FPGA system clock domain?
 

barry

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You've got two clock domains, SCLK and FPGA CLK. It doesn't matter how close or far apart they are in frequency, you still have to deal with it. Probably the easiest way is with a FIFO.

SCLK clocks data into a shift register. When a complete packet is received, write the shift register data to a FIFO using SCLK. Read from the FIFO using the FPGA clock.

Depending on speed, yes, you can use any GPIO pin as a clock input. Your timing analysis will tell you if there's a problem.
 

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SPI uses opposite edges to transmit and receive, so setup hold is generally easy to meet. Your timing constraints need to reflect the launch clock edge and the destination edge edge used for the transfer.

I would recommend using a global or local clock buffer for SCLK.

If you resort to not using a global or local clock routing and instead used fabric routing then you may end up with a design that intermittently fails to meet timing when you rebuild the design. I've seen this happen in designs as the shift register does not meet setup or hold on some of the bits due to large skew in the clock routing.
 

matrixofdynamism

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The uC SPI SCLK is 20MHz. The FPGA clock is 33MHz. I don't think I can sample the SCLK continuosly and then generate signals that detect rising and falling edge of SCLK and expect reliable operation since the FPGA system clock is not 4 times or more than the SCLK. Another issue is that the SCLK is not free running. It only toggles a few times when data is being transmitted.
 

barry

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The uC SPI SCLK is 20MHz. The FPGA clock is 33MHz. I don't think I can sample the SCLK continuosly and then generate signals that detect rising and falling edge of SCLK and expect reliable operation since the FPGA system clock is not 4 times or more than the SCLK. Another issue is that the SCLK is not free running. It only toggles a few times when data is being transmitted.

Reread post#2. You seem to be fixated on "sampling SCLK with the FPGA clock".

DON'T SAMPLE SCLK WITH FPGA CLOCK.

Again:

USE A FIFO
 

FvM

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It's clear that a shift register operated in the SPI clock domain is the appropriate method. Due to the relative low word rate, a simple handshake method with synchronizers can be used for consistent data transfer across the domain boundary.
 

matrixofdynamism

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ok, I can now see that using a DCFIFO with SCLK as one of the clocks is the only way left. This did not occur to me since the SCLK is not running all the time so it seemed strange to use it as a clock. The SCLK is coming from a microcontroller rather than a crystal so will have all sort of issues with clock jitter e.t.c.
 

barry

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"All sorts of issues with clock jitter"? Why? What "sorts of issues" do you foresee? And a FIFO is not the ONLY way, but probably the easiest for you.
 

FvM

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Due to the discontinuous SPI clock, DCFIFO is probably not the easiest way.
 

barry

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I disagree. Use the SPI SS as the FIFO write enable, and SPI CLK as FIFO WR clock. That's pretty simple.
 

FvM

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Sounds like a 1-bit wide FIFO. But how does it keep the frame information?

I was assuming a SPI receiver register and a word-wide FIFO.
 

barry

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Sounds like a 1-bit wide FIFO. But how does it keep the frame information?

I was assuming a SPI receiver register and a word-wide FIFO.
Ach, you're right. That's what happens when I post too early in the morning.

.
 

niciki

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Sounds like a 1-bit wide FIFO. But how does it keep the frame information?

I was assuming a SPI receiver register and a word-wide FIFO.
What if to use a different input-output clock and width ratio? 1-bit input, but 8 bit output FIFO with output clock 1/8 of the input clk?
 

barry

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What if to use a different input-output clock and width ratio? 1-bit input, but 8 bit output FIFO with output clock 1/8 of the input clk?
That means you have to use a serial-to-parallel shift register, shift in 8 data, write to FIFO. See post #2
 

niciki

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I don't have to use serial-to-parallel shift register. Look here (it comes from FIFO Generator v13.2, PG057 October 4, 2017):
1618007218626.png
 

FvM

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A mixed width FIFO can perform serial-to-parallel conversion and data transport between clock domains. It doesn't automatically sync the data to frame qualifier nCS and it's probably not simple to recover frame synchronization in case of missing/excess SCK edges. Due to discontinuous write clock and FIFO synchronization chain , SPI reception will be always one frame behind, unless the sender would send dummy clock cycles.

Shift register with handshake synchronization, as mentioned in post #6, still seems a better solution to me.
--- Updated ---

Here's a RTL view of the mixed width FIFO in Quartus

1618053650371.png
 
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