Advanced Member level 2
I need to design an SPI slave peripheral inside an FPGA that shall be used to communicate with a Microcontroller and configure the behaviour of the FPGA design. The SCLK and FPGA system clock frequency is close in range. This means that I cannot sample the SCLK continuously and use that to decide when to sample and shift the data from the SPI master. I have a few questions.
- If the SCLK input clock is almost of same order as the FPGA system clock? Does the clock signal connect directly into the FPGA registers? (b) If not then what is the alternative? I am in this situation where the FPGA system clock is not 4 times or more than the SCLK frequency.
- If (a) above is true then how do we write the timing constraints?
- The SCLK does not need to use global clock routing. Does this mean that any FPGA pin can be used for it?