How to creat a random data in verilog!

[test_out]

Hi,

I wouldlike to check my design, and I want to creat a random data stream 36 bit. How can I do?
Thanks

 

[yuenkit]

insert
$random
in your testbench

 

[no_mad]

hi,

The system task, $random, it can generates random number. It is a good practice to use it in the testbench to detect any hidden bugs in the design.

Ex.
// ur testbench
always @(posedge clock)
addr = $random(r_seed);

// r_seed is optional and is used to ensure the same random number sequence each time the test is run.

For more info, please refer to this book:
Verilog® HDL: A Guide to Digital Design and Synthesis
by Samir Palnitkar.

I think u can download this book from Edaboard.

Enjoy..

-no_mad

 

[woodyplum]

$random, the verilog LRM or IEEE standard should be the best reference

 

[sree205]

i'm not sure how u can generate a 36-bit random value. $random provides only 32 bit max value. what you could probably do is, concatenate it with a 4-bit counter

 

[jjww110]

to sree205,
you can use two random and combine them!!

 

[test_out]

Hi, jjww110

Can you explain more detail, how can I combine two random to form 36_bit random value?

Added after 19 minutes:

ah, I got it, thanks you!!

 

[Riddler]

use $random%(see_d) function
it will generate values betwwen -(see_d-1) to +(see_d -1)
To constraint to +ve values only
use {$random}%(see_d) so the values generated will be in the range 0 to (se_d -1)