Re: How to costraint clock generated by combination logic in
Dear rameshsuthapalli,
Thanks for your reply!!
I will try to explain my question in my best!!
For example:
https://obrazki.elektroda.pl/40_1164819451.jpg
For the DC script, I will write:
create_clock -name "sysclk" -period 10 "sysclk"
This will constrain FF1 & FF2. For FF3, the clock came from the AND2 gate.
ex: wire net3 = Q1 & Q2.
Since I don't the AND2 gate name when DC optima, I can't set clock constraint.
If I set create_generated_clock on Q1 or Q2 or both, it was unsuite. I had tried this
setting, the timing report wasn't what I expected. If I try to find the AND2
gate name, then set create_generated_clock on its output pin.
The timing report was what I expect.
Dear rameshsuthapalli, I hope you can understand what I want to say.
And pls kindly give me some suggestion!!
Thanks!!