How to costraint clock generated by combination logic in DC?

[copper230230]

In my RTL code, some FF were trigged by a clock source which was generated by combination logic. How to constrain the clock source in DC, since the DC can't set create_clock on the net! ( If force to constraint, warring message was shown )

1. Is it suggested to use "AND gate" to implement the clock source in the RTL
code. Then set_dont_touch this AND gate & create_clock in the DC?

2. Or is it suggested to set output port for A_clk since DC preserved the output
port of module and then create_clock on the output?

Which one was better? Thanks!!

For example:

wire A_clk = B & C;

always @( posedge A_clk or negedge rstb )
if( ~rstb )
cnt <= 8'b0;
else
cnt <= cnt + 1'b1;

 

[jcchan]

Re: How to costraint clock generated by combination logic in

i think option 2 is best for constraint.

 

[rameshsuthapalli]

hi all,

in my openion for dc u no need to tell the gated clocks definition.in default it will do analisys for the gated clock. if u r case is such that only B or C is clock and other is controll of the clock.then dc will do analysis of A in such that its period is B(clock).if ther is any path between the Aclock domain and B clock domain those paths r analyzed in such a way that the gate delay of the AND gate will be considered.

if u have still doughts please explain what r the B and C.i will try to help u.

regards,
ramesh.S

 

[copper230230]

Re: How to costraint clock generated by combination logic in

Dear rameshsuthapalli,
Thanks for your reply!!
I will try to explain my question in my best!!
For example:

https://obrazki.elektroda.pl/40_1164819451.jpg

For the DC script, I will write:

create_clock -name "sysclk" -period 10 "sysclk"

This will constrain FF1 & FF2. For FF3, the clock came from the AND2 gate.
ex: wire net3 = Q1 & Q2.
Since I don't the AND2 gate name when DC optima, I can't set clock constraint.
If I set create_generated_clock on Q1 or Q2 or both, it was unsuite. I had tried this
setting, the timing report wasn't what I expected. If I try to find the AND2
gate name, then set create_generated_clock on its output pin.
The timing report was what I expect.

Dear rameshsuthapalli, I hope you can understand what I want to say.
And pls kindly give me some suggestion!!
Thanks!!

 

[dcreddy1980]

Re: How to costraint clock generated by combination logic in

Hi,

I think u can just instantiate u r "and gate" as a seperate module and apply a "dont_touch" on this particular cell...then DC wont optimize u r "and gate"....Hope u got what i am trying to say??

Regards,
dcreddy

 

[copper230230]

Re: How to costraint clock generated by combination logic in

Dear dcreddy,
Thaks for your reply!!
I can understand your method.
But if I transfer from one tehc libirary to another tech library, the AND gate will
modify again & again since the AND gaet name was different in every tehc library. It was inevitable, right?
Why you don't suggest method 2 ? If I do so, I can focus on the script without need to check the AND2 name? If there are any consideration for APR or STA??
Thanks for your answer!!

 

[blanket]

Re: How to costraint clock generated by combination logic in

why not create an edge detecting pulse on the A_clock transition and then use an enable flop with normal clock for the logic??

removes all issues captured in this thread - isn't it?

-b

 

[rameshsuthapalli]

hi dcreddy,

can u draw the diagram with respect to the sysclk.
in my view the clock appalied to the ff3 is not the clock that is a combinations clock of one clock and the controlled logic. it is clock derived through the sequential circute so u have to define the clock as a derived clock.

for dc u have to tell
the source clock name and source clock generation point and the derived clock name and the derived clock source point and the derivation factor.

regards,
ramesh.s