How to convert designs from FPGA to ASIC?

[ldhung]

convert fpga to asic and ram

Hello,
If I have designs on FPGA, using VHDL or Verilog, how can I convert my designs on FPGA to ASIC ? Which tools I can use to convert from FPGA design to IC design ?
Thank you

 

[JesseKing]

convert fpga to asic and how to

No tool can directly change FPGA design to ASIC, you can use std. cell synthesizer, such as dc, bg to synthesize your original HDL code to gate netlist, and use pr tool to implement it.

 

[linuxluo]

hi,
if you using altera or xilinx fpga, you can ask their AE to convert your Fpga to ASic produced by them. still using the fpga netlist , this shorten TTM.

 

[senthilkumar]

use the xilinx tool to convetrt the design

 

[ldhung]

Which xilinx tool used to convert ? ISE?
Can I convert my design to EDIF, then import EDIF to IC tools. But which Cadence IC tools is used?

 

[zysmith]

after verificatiing RTL, employ ASIC flow.
backend of ASIC is far different from FPGA.

 

[srik_naidu]

hi,
remove the rams and dplls from the fpga design since rams and dplls not synthesized in asic synthesis.provide external interface from the fpga design to those when u r going for the asic synthesis.


with regards,
srik.

 

[power-twq]

I think you must convert FPGA to asic by yourself.

1) change FPGA ram to ASIC ram.

Hello,
If I have designs on FPGA, using VHDL or Verilog, how can I convert my designs on FPGA to ASIC ? Which tools I can use to convert from FPGA design to IC design ?
Thank you

 

[lijian_18]

I recommend use DC to resynthesis the whole design. Only in this way you can get more optimized circuit. What you need to do is only convert ROM, RAM and other analog IP to corresponding ASIC IPs.