How to convert C++ code to VHDL?

[555lin]

I need to transfer the c++ code to make a VHDL program in
Xilinx ISE environment.Xilinx ISE doesn't support multidimension arrays. How can I adapt the code of the c++
program where a 2D array is used and many 32 cycles are required?

 

[gliss]

vhdl quetion

In VHDL convert it to a 2D memory array.

 

[avimit]

array port vhdl

Firstly its hard to believe that ISE does not support multi-dim array. So pls double check.
And if it is true, then you will have to flatten your 2D arrays into a 1D array.
For example a 2D array say of n elements which contains say m element each should be flatten into a mxn 1D array.
Kr,
Avi
http://www.vlsiip.com

 

[vomit]

vhdl 2d array port

There are 2 kinds of multidimensional arrays in VHDL: the real multi-dimensional array

type myarraytype is array(dimension1, dimension2) of elementtype;

and the array composed of another array

type arrayofarraytype is array(dimension1) of arraytype;

Does ISE only reject the multidimensional array? Perhaps you can work around it using an array-of-array?

 

[555lin]

vhdl array port

please show the correct syntax for example for
a [16,32] array

 

[vomit]

vhdl port array

a [16,32] array of what type of element? Let's call the it "elementtype" for the moment.

in C, the last dimension is contiguous in memory. So let's try to simulate that:

type t_myarray is array(0 to 31) of elementtype;
type t_my2darray is array(0 to 15) of t_myarray;

If elementtype is "std_logic" then you can replace t_myarray by

subtype t_myarray is std_logic_vector(0 to 31);

By the way: to read an element from
signal myarraysig : t_myarray;
you must write 2 sets of parentheses:
myarraysig(13)(24)

 

[wangkaust]

port array in vhdl

In VHDL, you can use 2D array in the port.
Just manually expend them into 1D array.
To use it internally, I think it is OK with ISE.