how to control the register output name in DC

[chico]

A is a 6bits register, in the output netlist, the registers' output are n12,n32,n35,etc. I want the result are A[5], A[4] …… A[0], what should I do? Thank you!

 

[stormwolf]

you can try command as below:
set hdlout_internal_busses true
set bus_inference_style "%s\[%d\]"
change_names -rules verilog -hierarchy

 

[chico]

Thank you stormwolf, these command are exist already. I find this phenomena is on QN output only register, and the Q is disapper, how to prevent DC optimize these Q ouput disapper?

 

[tarkyss]

try this command
set verilogout_show_unconnected_pins true