How to control the Capacitance & Resistance in post layout extraction ?..

[Blue Hawk]

Hi all,

In the post layout extraction ( pex extraction ), if there's any problem occurs in pex means, we need to vary ( increase or decrease the resistance & capacitance ) in some signal lines..
I think we can reduce the resistance by using an higher metal instead of using metal 1 or 2.. Likewise, I need to know that " How to increase or decrease the capacitance & resistance in any signal lines ? "..

Thanks in advance..

 

[sarge]

Hi

I think we can reduce the resistance by using an higher metal instead of using metal 1 or 2

You can reduce resistance in such manner, if higher metal has smaller square resistance = higher thickness (and don't forget about resistance of vias), with using higher metals you also decreasy parasitic capacitor to the ground.
Best choise is using top metal, it usually has relative high thickness.
Other way 1: Make the metal wire wider - decreasing resistance, increasing capacitance
Other way 2: Stacking metal wires on some layers - decrease resistance, and i think that capacitance stay relative equal to one-metal parasitic capacitance (but i'm not sure about this)

This is only my thoughts about your questions

 

[jdwk]

Old old thread, but the only one I can find that is actually relevant.

Other way 1: Make the metal wire wider - decreasing resistance, increasing capacitance

In response to this. Wouldn't widening the metal increase the capacitance at the exact same rate as it reduces resistance, and the RC value would be exactly the same?

Since the capacitance increases, the load on the driver increases which slows down the cell and increases the transition time, making the overall delay slower. So wouldn't you want the least wide highest metal available to decrease overall delay?

In simulation and on silicon, the resistance plays a huge role in the effective capacitance, particularly on high fanout nets, but not sure what carries more weight in these situations. It probably is net dependent.

 

[erikl]

Wouldn't widening the metal increase the capacitance at the exact same rate as it reduces resistance, and the RC value would be exactly the same?

This is surely true for initially already wide wires. For min. width wires in sub-tenth-micro technologies however, the fringe part plays an essential - if not the main - role for cap/length. As the fringe-part per length doesn't change, increasing the width of min. or low width wires may decrease the RC delay of the connection, as the capacitance increases less than proportional to width.

 

[jdwk]

That's exactly the kind of answer I was looking for. Thanks.