How to constrait two data signal for balance delay time by DC or STA

[Matthewli]

like a two related signal to the pad.
we want to make sure these two signal delay time to the pad is slimilar or balance. the skew of these two signal is not too bigger.

Which constraint we need to add? Does set_max_delay Okay or set_data_check? Which one is better?

thanks a lot.

 

[rca]

Set_data_check is here for that, but you could add some specific report during the sta, the question is do you want to add a constrains or only add a check during the sta?

 

[Matthewli]

For DC constraints, which one ? For STA, what special report here? thanks