How can we ensure that the clk and data sent from the SD HOST to the device meet the setup and hold time requirements of the device?

[wt1821926020]

So far, it only requires that the receiving side of the HOST uses a DLL to receive read data in the high - speed transmission mode. There is no requirement for using a DLL for phase - adjustment on the sending side. Then, how can we ensure that the clk and data output to the device can meet the setup and hold time requirements?

 

[sky_siliconthink]

Something to check, maybe:
1): Check datasheet of the sending part. It should have time value to define it's output data delay. Then use this tiem value to constraint your input ports at receiving part (set_input_delay).

2): If no time value from sending part. You may need a trainning phase, something similar to the trainning phase for DDR controller. At this phase, you have to adjust the delay of each bit of data, and make sure the setup/hold timing is meet.

More info on STA and DC synthesis: https://www.udemy.com/course/digita...-synthesis/?referralCode=F99007C1E5B740E11E03

 

[dick_freebird]

You should work on a spec alignment basis at both ends and scrub them together for an "interface control document line item".

If RX is standard then that end should be known and the rest, you own.

If it's a one-off or bleeding edge, must get them to declare.

Clock edge centered in TX data eye seems like demanding least effort for best BER but setup alone, might ask for later - until you start to see the other end of the BER statistical bathtub.

 

[D.A.(Tony)Stewart]

It depends on your FSM design in RTL.

How do I avoid setup and hold time violation?

How do I avoid setup and hold time violation?

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