[SOLVED] Are these two SystemVerilog statements equivalent and do they work as I expect them to?

[Plexiglas1]

I'm trying to minimize logic and make the (ASIC) synthesis tool merge the 2'b11 case's logic with the previous ones, as I don't care about that case.
I know I can make the second-to-last statement the default, but that might not be optimal in terms of logic in the general case.
This is a minimal example of what I'm trying to do, so don't worry about the specifics of this concrete example.
Are the statements equivalent and are they doing what I want them to?

case(cond)
  2'b00: result = v1;
  2'b01: result = v2;
  2'b10: result = v3;
  default: result = 'x;
endcase

unique case(cond)
  2'b00: result = v1;
  2'b01: result = v2;
  2'b10: result = v3;
endcase

 

[dave_59]

Actually, for the code you wrote the first case statement would be equivalent to both a unique case and a priority case statement. You are stating that all case items have been specified and all other unspecified expressions are a don't care. SystemVerilog would generate a warning if an unmatched expression ever occurs.

 

[ThisIsNotSam]

give it a try with our synthesis tool of choice with a MWE. if you have a mux4 in your library, all these tricks might yield the same gate count and you wasted brain power but saved nothing. (I assume you know how to avoid latches for your case stmt, so that shouldn't play a role.)

 

[Plexiglas1]

...if you have a mux4 in your library, all these tricks might yield the same gate count and you wasted brain power but saved nothing.

That's why this is a minimal case and I'm talking about the general case.
For example: you have an enum with 17 values, and only want cases for 5 of them while the rest of them should be "don't care".

--- Updated Feb 20, 2025 ---

Actually, now I realize I don't always want to use the unique case, because it throws warnings in the simulation when other enum values are used, even if I don't care about them in this block of code.
So I'm left with the second part of the question, does 'x in the default case optimize in cases such as I described above?

 

[dave_59]

Use unique0 if you don't care if other enum values are used. All three keywords unique, unique0, and priority, tell the synthesis tool tell the synthesis tool that alll other case items are don't cares.

 

[Plexiglas1]

Use unique0 if you don't care if other enum values are used. All three keywords unique, unique0, and priority, tell the synthesis tool tell the synthesis tool that alll other case items are don't cares.

Oh yeah, forgot about unique0.
Thanks for the help!