How to constrain the design clock with Design Compiler?

[feel_on_on]

CLK1,CLK2,CLK3 was selected by a multiplex,then generate CLK4,CLK4 frequency was divided ,and get CLK5,.....

how to constraint the design clock with Design Compiler

 

[sree205]

question on DC

u can look up these commands : create clock and set_propagated_clock.

 

[moorehuang]

question on DC

CLK5 should be set as generated_clock

 

[rsrinivas]

question on DC

clk4 should be gated clk
and as previously said clk5 is generated clk
u can use create_generated_clk command and give the divide factor.
u can see the generated clk after synthesis in ur report from report_clk command

 

[sumit_techkgp]

question on DC

Propagate the clock