how to connect bulk to a different point in layout

[nozone]

In the cmos rf circuits, we have a stacked design, if I want to connect the bulk for upper nmos transistors to a higher voltage instead of gnd, what's the best way of connecting them in the layout? should I use a dnw+pwell?

thanks in advance.

 

[nozone]

help please

 

[safwatonline]

u must have a triple well process,pwell inside a deep nwell

 

[Brittoo]

In the cmos rf circuits, we have a stacked design, if I want to connect the bulk for upper nmos transistors to a higher voltage instead of gnd, what's the best way of connecting them in the layout? should I use a dnw+pwell?

thanks in advance.

Hi nozone

U could go ahead with DNW for sure. That way yoyu could connect the nmos to a voltage different from gnd voltage.

Regards
Brittoo

 

[nozone]

yes, we have triple well process, so I will just do it. thanks for all the answers

 

[hazemafify]

What is the layout tools you use?

 

[fixrouter4400]

yes, we have triple well process, so I will just do it. thanks for all the answers

Definitely you must put the nmos within DNW also adding double guardring a substrate ring inside and an NWELL ring outside then cover the whole nmos transistor with DNW layer...following the right rule dimension for the DNW layer.

 

[gafsos]

DNW is used as a well for PMOS. It also serves as an isolation from onther type of devices. In a twin well process, the subsrate serves as the P well of NMOS.
Deep N-well is a special layer used to supress Substrate Noise coupling injected by Digital Logic in Mixed Signal environment.During the digital logic switches from high to low or viceversa it injects noise which will be propagated through the substrate.Since the sensitive Analog circuit will be on same substrate, the noise can degrade the performance of the analog circuit.For example this noise can be amplified by an op-amp and its output will vary.
gafsos

 

[bocinverson]

how to contact dnw to vdd?
thanks?

 

[varma_cs012]

Just draw a N/W tap for it and connect it to VDD.
When ever N/W is there in DNW those two or shorted.
Please let me know if u have still any problem. Thank You.

Varma.

 

[jecyhale]

In the cmos rf circuits, we have a stacked design, if I want to connect the bulk for upper nmos transistors to a higher voltage instead of gnd, what's the best way of connecting them in the layout? should I use a dnw+pwell?

thanks in advance.

I think you can connect the dnw to a higher voltage directly.

isn't it?

 

[Brittoo]

In the cmos rf circuits, we have a stacked design, if I want to connect the bulk for upper nmos transistors to a higher voltage instead of gnd, what's the best way of connecting them in the layout? should I use a dnw+pwell?

thanks in advance.

I think you can connect the dnw to a higher voltage directly.

isn't it?

Hi jeychale

What do you mean by connecting to high voltage directly?? You would need to put a NW tap which would bias your DNW. Could you please clarify your statement?

Regards
Brittoo

 

[RFDE]

actually , RF mosfets in some technologies have 5 terminals in layout ; 3 known terminals , 1 bulk terminal & a vdd terminal for the guard ring